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3D IC Industry Summary

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As an active proponent of three-dimensional integrated circuits (3D ICs) for nearly a decade, Tezzaron® is gratified to see the near-universal recognition of this exciting technology. As more and more organizations invest in 3D IC research and development, Tezzaron welcomes the expanding opportunities for partnership and collaboration in 3D electronics.

This page provides a summary of the current state of 3D ICs. Other 3D structures such as MEMS and SiP are not addressed.

For papers and articles discussing 3D ICs, we recommend the Literature Page at the website of the 3D-IC Alliance.

The information below is gathered from trade publications, websites, and conference presentations. Please alert us to any corrections and updates at webmaster@tezzaron.com.

Page contents:

bullet3D IC Products and Services
bullet3D IC Tools and Equipment
bullet3D IC Research
bulletMarket Research, Analysis, Consulting, Reporting

3D IC Products and Services

bulletTezzaron

Wafer stacking Cu-Cu thermo-compression and standard "bulk" wafers; thru-silicon vias (TSV). 2004: Successfully produced 6 different two-level devices. Four-wafer test stacks have been created; electrical connectivity has been verified in 3-wafer stacks; bulk wafers have been stacked with SOI wafers. Business offers 3D products, joint ventures, and licensing. (IAB 2004; 3-D ASIP 2004 thru 2009; VMIC 2004 thru 2008; Semicon West 2006; 3D-SIC 2007; IMAPS 2007 thru 2009, Pixel 2008, GBC 2009, Front-End Electronics 2009, BrightSpots 2009)

bulletZiptronix

Die-on-wafer stacking using room-temperature covalent bonding (silicon fusion) and direct oxide bonding. A two-wafer test stack was created, but primary emphasis is integrating known good dies (KGDs) onto wafers, producing two-level "chip pairs." Business offers heterogeneous substrates; chip stacking; custom 3D services. 3D SoC announced in 2005. (3-D ASIP 2004 thru 2009; MRS 2006 & 2008; 3D-SIC 2007, Front-End Electronics 2009)

bulletSanDisk (formerly Matrix; SanDisk purchased Matrix in 2006)

Permanent 3D memories, one-time-programmable (OTP); multiple memory layers built on a single wafer. Memories with eight layers were announced in 2001, first shipped in 2003, now shipped in volume. (Matrix paper at VMIC 2005)

bullet ZyCube

Wafer-on-wafer stacking with injection glue bonding, buried vias (tungsten or polysilicon), and "micro-bump" connectors. (3-D ASIP 2005, 2006, 2008; MRS 2008, IMAPS 2008, Pixel 2008)

bulletVertical Circuits

Die-on-die stacking; commercial memory and custom devices; vertical connectors applied to die edges. (3-D ASIP 2004,  2007; GBC 2009)

bulletFlipChip International

3D-related services: wafer bumping, die placement, backgrinding, etc. (3-D ASIP 2006, IMAPS 2008)

bulletAmkor

3D chip packaging, bumping, die stacking; working with IMEC (3-D ASIP 2004, 2006 thru 2009; GBC 2009, IMAPS 2009)

bulletAlchimer

Licenses electrochemical deposition technology for TSV. (3-D ASIP 2008, MRS 2008, Sematech 2008, Semicon West 2009)

bulletALLVIA (and Tru-Si Technologies)

Through-silicon via (TSV) "drill-and-fill" via services including patterning, etching, thinning, die stacking. TSV R&D services; advanced vertical interconnects; custom through wafer via manufacturing and testing; low volume production runs. (3-D ASIP 2006, 2008)

bulletaustriamicrosystems

Provides TSV manufacturing for its foundry customers.

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3D Tools & Equipment (in alphabetical order)

bulletAjisso

Die placement, alignment, & bonding equipment

bulletAviza

Wafer processing equipment to create TSVs. (3-D ASIP 2008)

bulletChartered Semiconductor

Provider of TSV-enabled wafers.

bulletCoventor

Modeling tools for 3D silicon (3-D ASIP 2007)

bulletDynatex

Materials and equipment for 3D - bonders, adhesives.

bulletEV Group (EVG)

Equipment for alignment and bonding, both chip-to-wafer and wafer-to-wafer. (3-D ASIP 2004 thru 2009, Semicon West 2005 & 2009, IMAPS 2007 & 2008, WLP 2008, BrightSpots 2009, Semicon West 2009)

bulletHenkel

Ablestik™ adhesives for die attachment.

bulletJavelin Design Automation

3D stacked IC design tools and technology. Working with IMEC and Qualcomm.

bulletLam Research

Etch system for Thru-Silicon Vias (TSV). (3-D ASIP 2007, 2008.)

bulletLaurier Inc.

Die-to-wafer and wafer-to-wafer bonding equipment. (3-D ASIP 2006)

bulletMicro Magic

MAX-3D layout editor for stacked chip designs.

bulletNEXX Systems

Process tools for 3D packaging; electrochemical copper deposition, etc. (Also does interconnect research with SEMATECH.) (3-D ASIP 2008)

bulletPVA TePla

Wafer thinning by smooth remote plasma etching.

bulletR3Logic

EDA tools for 3D integrated circuit design and analysis; 3D circuit design services; working with Micro Magic, DARPA, STMicroelectronics, CEA-LETI. (VMIC 2005, 3-D ASIP 2006, 2008, 2009; 3D-SIC 2007, DATE 2009)

bulletSemitool

Copper interconnect, wafer prep, wafer level packaging. (IMAPS 2007, 2008, 2009; 3-D ASIP 2008, GBC 2009, DATE 2009)

bulletSurface Technology Systems (STS)

Etch, deposition, and sealing systems. (3-D ASIP 2008)

bulletSUSS MicroTec

Aligners, wafer and device bonders, thin-wafer processes, temporary bonding & debonding, other 3D packaging tools. (3-D ASIP 2005 thru 2009; IMAPS 2007 & 2008)

bulletTegal

Plasma etch and deposition systems, silicon DRIE tools. (3-D ASIP 2008)

bulletUltratech

Lithography steppers for 3-D technologies. (Semicon West 2009)

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3D IC Research (in alphabetical order)

bullet3D-IC Alliance

Consortium of integrated circuit designers, developers, and manufacturers; promotes standards for three-dimensional integrated circuits (3D ICs).

bullet3D Plus

Research on stacking rebuilt wafers. (IMAPS 2008)

bullet3D-ROM

Research on 3D read-only memory chips.

bullet3M

Research on wafer thinning, stacking. 2009, research (with SUSS) on temporary bonding.

bulletAccretech

Research (with SEMATECH) on wafer thinning & thin wafer handling.

bulletAlbany NanoTech

Research on wafer stacking, interconnects, and wafer-scale heterogeneous 3D integration; partner with SEMATECH and many other research groups. (3-D ASIP 2005)

bulletAlcatel (formerly Lucent)

Research on thru-silicon vias (TSV). (IMAPS 2007 & 2008, DTIP 2008, 3-D ASIP 2008)

bulletAmkor

Research (with IMEC) on 3D integration technology based on wafer-level processing. (IMAPS 2008)

bulletApplied Materials

Research (with EMC-3D) on thru-silicon via (TSV) process flow; 2009, announced research (with EVG and ITRI) on wafer thinning and bonding.

bulletAnadigics

Research on 3D cell phone transmit module. (3-D ASIP 2004)

bulletASE Global (ASE Group)

3D-related packaging and TSV research (3-D ASIP 2008, Semicon West 2009)

bulletASET (Association of Super-Advanced Electronic Technologies)

Japanese consortium. Developed a bulk wafer stacking process with Cu-Sn eutectic bonds and 10 um vias, successfully demonstrated on CCD wafers. (Effort ended in 2004.) Research on 3D sensors (with Sanyo Electric), chip-to-chip bonding, technology used in CCD camera; research on design, test, and simulation of 3D structures. (3-D ASIP 2004 & 2007; 3D-SIC 2007).

bulletAtotech

Research (with Albany & SEMATECH) in metallization of TSVs.

bulletBeSang

Research on 3D memories and image sensors, using wafer stacking with metal bonding. (3-D ASIP 2006 & 2009)

bulletBrewer Science

Research (with EVG) on bonding/debonding technologies (3-D ASIP 2008, WLP 2008)

bulletBrookhaven National Lab

Research on 3D-IC sensors; hosted & chaired Front-End Electronics 2009.

bulletCadence Design Systems

Research on 3D IC design tools. (3-D ASIP 2004, 2005, 2007)

bulletCEA-Leti

Research on wafer-to-wafer and die-to-wafer stacking; self-assembly, low temperature direct bonding, and capillarity; 3D smart cards. (3-D ASIP 2005, 2006, 2008, 2009; IMAPS 2007 thru 2009, IITC 2007, MRS 2008, WLP 2008, DATE 2009, Semicon West 2009)

bulletCEA-IRFU-Saclay

Research on 3D pixel sensors (Front-End Electronics 2009)

bulletCornell

Research on 3D wafer-level low-temperature circuit layering using SOI wafers; 3D electronic integration; crosstalk & heat issues; 3D FPGAs. Four-layer stack announced in 2005. ( VMIC 2004 thru 2007)

bulletDARPA  (Defense Advanced Research Projects Agency)

Funds special research, including 3D IC process technology, heterogeneous integration, 3D architectures, stacked FPGAs, and a "vertically interconnected sensor array" (VISA) with die-on-wafer stacking and polymer adhesive bonding. Funded two "multi-project wafer" (MPW) runs, each with 3 stacked wafers; preliminary results in 2006 show some parts are functional. Funding new MPW runs in 2009. (3-D ASIP 2004 & 2005; VMIC 2007)

bulletDatacon

Research (with EMC-3D) on die bonding. (IMAPS 2008)

bulletDisco

Precision processing tools for grinding, polishing, dicing. (3D-SIC 2007, IMAPS 2009)

bulletDuke University

Research on 3D ICs (DATE 2009)

bulletDuPont Electronics

Research on materials for WLP, 3D, and TSV. (IMAPS 2008)

bulletElpida Memory

Research on high-density memories, including a 3D "bio-brain" concept; memory stack will use via-first construction, back-bumping,  interposer layer, and interface chip. (3-D ASIP 2006, 3D-SIC 2007)

bulletEMC3D (Semiconductor 3D Equipment and Materials Consortium)

A consortium of tech, tool, and materials companies; research into lower costs for chip stacking with thru-silicon vias. 2009: announced program extension to July 2011, expanded goals include both via-last and via-middle techniques for reliability and even lower cost. (IMAPS 2007 & 2009)

bulletEndicott Interconnect

Research on Z-axis interconnect. (DATE 2009)

bulletESI (Electro Scientific Industries)

Research on 3D-IC packaging and tools. (Semicon West 2009)

bulletEverspin

Research on TSV. (VMIC 2008)

bulletFCRP (Focus Center Research Program, also MARCO)

Funds and operates research centers; its Interconnect Focus Center participates in 3D efforts. (3-D ASIP 2004)

bulletFermi National Accelerator Laboratory (Fermilab)

Research on 3D components, particularly sensors and detectors; sponsors multi-participant research projects; sponsored Pixel 2008; 2009, sponsoring a 3D MPW (multi-project wafer) with other particle detector groups. (Front-End Electronics 2009)

bulletForza Silicon

Research on 3D imagers. (ISSCC 2009)

bulletFraunhofer IZM

Research on vertical system integration, chip-in-polymer stacking, die-on-wafer stacking with solder bonds, flexible substrates, and 3D components (sensors, CPUs, memories). New research facility, ASSID, announced in 2009. (3-D ASIP 2005 & 2007, MRS 2006, 3D-SIC 2007, IMAPS 2007 thru 2009; IITC 2008, VMIC 2008, DATE 2009)

bulletFreescale Semiconductor

Research on wafer-to-wafer bonding techniques. (3-D ASIP 2005, 2006, 2008; IITC 2007; IMAPS 2008 & 2009; VMIC 2008)

bulletGE Global Research

Research on stacking techniques and 3D sensors. (3-D ASIP 2004)

bulletGeorgia Tech

Research on physical design, design tools, micro-architecture, thermal and interconnect issues, and testing in 3D ICs. Research (with SRC) on 3D interconnect and packaging. (VMIC 2008, DATE 2009)

bulletGigascale (Academic collaboration)

Research on 3D architectures, thermal issues, routing, reliability, etc. Many papers and publications.

bulletGSA (Global Semiconductor Alliance)

Research to foster adoption of 3D, especially interfaces and standards. (3-D ASIP 2009)

bulletHD MicroSystems

2009: Research on adhesives for temporary and permanent wafer bonding.

bulletHonda Research Institute (HRI)

Research on 3D integration technologies, especially wafer stacking with TSV. (3-D ASIP 2007, IMAPS 2008 & 2009)

bulletIBM

Research on wafer-level stacking of SOI wafers using oxide fusion bonding; Cu bonding; and die-on-wafer stacking, mounting small dies onto a larger "motherboard" die. Interconnects have been created on 4-wafer mechanical stacks. In 2007, announced a chip-stacked power amplifier with 100 direct metal connections. Other research on 3D design tools, test structures, methodology, process, infrastructure, TSV. (3-D ASIP 2004, 2005, 2007-2009; VMIC 2005 thru 2008; MRS 2006; 3D-SIC 2007; IMAPS 2007; SEMATECH 2008; GBC 2009)

bulletIME A*STAR (Institute for Microelectronics)

Research on many aspects of 3D IC technology including fluidic cooling, microbumps, bonding, die stacking, optical interconnects, etc. (EPTC 2008)

bulletIMEC (Interuniversity MicroElectronics Center)

Research on 3D imaging systems, 3D approaches and enabling technologies, including design issues. Runs APIC center (with other companies) to study interconnect. 2007, demonstrated wafer stacking with TSV; 2008, demonstrated die-on-die stacking with TSV. 2009, die-to-wafer copper bonding. (ISSCC 2004, 3-D ASIP 2005, 2006, 2008; IITC 2006, VMIC 2007, MRS 2008, GBC 2009, DATE 2009, Front-End Electronics 2009, ECTC 2009)

bulletInfineon

Die-on-die "chip sandwich" stacking, using diffusion soldering, micro-bump bonding. Technique demonstrated in 2002; prototype security chip-card demonstrated November 2004; chip-stacked tire sensor in 2009. Also two-level die-on-wafer memory stacking and deep vias (with Fraunhofer). (3-D ASIP 2004 & 2007, MRS 2006, 3D-SIC 2007, ISSCC 2009). 

bulletIntel

Research on stacking, 3D interconnects, 3D components, copper bonding, design issues. Simulations of two-level processors indicate 15% speed improvement plus 15% power reduction. 2007, exploring through-silicon vias and 3D Flash. Also, research on stacking memory onto processor. (VMIC 2004 & 2008, MRS 2006, 3-D ASIP 2007 & 2008; GBC 2009, IMAPS 2009, Semicon West 2009, 3-D ASIP 2009)

bulletInstitute of Subatomic Research (IReS), France

Research on 3D-IC active pixel sensors (Front-End Electronics 2009)

bulletipdia (spun off from NXP Semiconductor in 2009)

 Research on integrated passives in 3D ICs. (IMAPS 2008, 3-D ASIP 2009)

bulletIrvine Sensors

Research on 3D IC process technology and thermal issues, 3D modular system integration, interconnects by die-edge metallization and thru-silicon (not thru-die) vias; 3D imagers. (3-D ASIP 2004 & 2005, 3D-SIC 2007, VMIC 2007 & 2008, IMAPS 2008, ISSCC 2009)

bulletIsonics

Research (with EMC-3D) on wafer thinning for 3D stacking.

bulletJacket Micro Devices

Research on 3D integration via Multi-Layer Organic (MLO™) technology. (IMAPS 2008).

bulletJazz Semiconductor

Research on models, tools, & support for 3D integrated designs. (3-D ASIP 2006)

bulletKAIST (Korea Advanced Institute for Science and Technology) 

Research (with Georgia Tech and Fraunhofer) on interposer layers for 3D iCs.

bulletKINIK Company

Research in substrates for vertical interconnect. (VMIC 2006)

bulletLaboratory for Physical Sciences (LPS, U. of Maryland)

Research into 3D for high performance computing; 3D interconnect; heterogeneous integration with covalent bonding; aluminum through-silicon vias have achieved aspect ratios of 16:1. (3-D ASIP 2005, VMIC 2006) 

bulletLaserfacturing

Research on laser processes for creating TSV.

bulletLincoln Labs (at MIT)

Research on three-layer SOI wafer bonding with silicon handle, low-temperature oxide bonding, and W vias done last; participated in several DARPA MPWs; 3D image sensors and radar sensors; first image sensor tests in 2005; reported working  devices in 2008. (3-D ASIP 2005 & 2009, VMIC 2006 & 2007, MRS 2006 & 2008, ISSCC 2009)

bulletLintec

Research on adhesives for 3D ICs.

bulletLSI-EPFL (Integrated Systems Lab, Federal Polytechnic of Lausanne)

 Research on clock and power distribution in 3D ICs (DATE 2009)

bulletMax-Plank Institute

Research on 3D-IC high-energy particle detectors (Front-End Electronics 2009)

bulletMCNC Research & Development Institute

Research on through-wafer 3D vertical interconnect (copper and optical), integrated passives, heterogeneous integration, vertical sensor arrays; working on various government and corporate programs. (3-D ASIP 2005)

bulletMicroChem

Research in adhesives for 3D ICs. (IMAPS 2008)

bulletMicron

Research on 3D memory using thru-wafer interconnects, a redistribution layer, solder balls, and epoxy encapsulation. Demonstrated 2-die stack. (MRS 2006, 3-D ASIP 2008)

bullet MIT

Research on 3D IC layout methodology, wafer stacking, high-density interconnect, copper bonding, oxide fusion bonding, using various types of wafers. Two-wafer stacks were announced in 1999; sensor design in 2001; four-wafer stacks in 2005. (IAB 2004; 3-D ASIP 2004 & 2005; MRS 2006; 3D-SIC 2007)

bulletNASA-JPL

Research on 3D stacking, sensors, memories, and packaging. (3-D ASIP 2004)

bulletNational Technology University, Singapore

Research on hybrid copper/ILD bonding. (VMIC 2008)

bulletNEC Electronics

Research on chip stacking, TSVs, 3D memory. 2009: announced nickel TSVs. (ISSCC 2009, Semicon West 2009)

bulletNextreme

Research on thermal management for 3D ICs

bulletNEXX

Research (with SEMATECH) on 3D interconnect.

bulletNorth Carolina State University

Research on 3D interconnect networks, architectures, & design rules. Working with DARPA; SRC award for research. (VMIC 2006 & 2007, 3-D ASIP 2006, 2008, 2009)

bulletNorthrop Grumman Space Technology

Research on IR thermal microscopy for 3D circuits. (IMAPS 2008)

bulletNXP Semiconductors - now IPDIA

 

bulletOerlikon Balzers

Research on thru-silicon vias (TSV). (WLP 2008)

bulletOptomec, Inc.

Research on using Aerosol Jet® material deposition system for vertical interconnect.

bulletPactech LLC

Research on wafer-level bumping and assembly (Front-End Electronics 2009)

bulletPenn State University

Research into 3D design and toolsets. (3-D ASIP 2006, DATE 2009)

bulletPhilips Applied Technologies

Research into TSVs, including filling with Cu pastes (MRS 2008)

bulletPowertech Technology (PTI)

Research on 3D IC packaging technologies (announced 2010)

bulletPTC

Research on 3D IC design management and flow, thermal issues, verification and synthesis tools; lead contractor for DARPA project (2004).

bulletPurdue

Research on silicon layering, epitaxial growth.

bulletQimonda

Research on 3D memory with TSVs.

bulletQualcomm

Research (with IMEC) on 3D design tools & technologies. (3-D ASIP 2008, GBC 2009, DATE 2009, Semicon West 2009)

bulletRensselaer Polytechnic Institute (RPI)

Research on wafer stacking/bonding/thinning with standard wafers and/or SOI; dielectric adhesives for low-temperature bonding; magnetic alignment; copper bond pads; 3D power delivery; 3D SOI SRAMs; 3D optical interconnect. Interconnect process announced in 2003. (3-D ASIP 2004 thru 2007; VMIC 2004 thru 2008; MRS 2006; IMAPS 2008 & 2009)

bulletReplisaurus / S.E.T.

Research (with IMEC) on die-to-die and die-to-wafer bonding and (with CEA-Leti) on metal processes for 3D. (Semicon West 2008, 2009)

bulletReveo

Research on multi-layer memories, wafer-scale stacking. (3-D ASIP 2004, IMAPS 2008)

bulletRohm and Haas (RHEM)

Research (with IBM) on novel materials for 3D ICs. (GBC 2009, IMAPS 2009)

bulletRTI International 

Research on 3D die-to-wafer integration with polymer and Cu/Sn bonding; polygeneous integration; vertically integrated sensors and coherent light devices; working with DARPA. (3-D ASIP 2005 thru 2009; MRS 2006 & 2008; 3D-SIC 2007; VMIC 2007; IMAPS 2008, Pixel 2008)

bulletRudolph Technologies

Research (with SEMATECH) on process characterization to improve process control for manufacturing of stacked 3D ICs, especially TSV production.

bulletSamsung

Research on chip-on-chip and chip-on-wafer stacking for high-density memory; thru-silicon vias (TSV), micro-bumps. 8-chip NAND stack (prototype) announced in 2005; Flash and DRAM prototypes in 2006; 4 level chip-stacked DDR3 in 2009. (3-D ASIP 2005 thru 2007, ISSCC 2009)

bulletSandia National Labs

Research on tungsten TSV. (ECTC 2009)

bulletSanyo

Research on 3D sensors.

bulletSanyu Rec

Research on filling TSVs.

bulletScanimetrics

Research on testing & monitoring 3D assembly. (3-D ASIP 2008)

bulletSEMATECH (R&D Consortium)

Research on 3D interconnect, identified as a "top technical challenge" in its International Technology Roadmap for Semiconductors (ITRS) for 2005. Organized symposiums in April 2004, June 2005, many other conferences. 2007, working on industry roadmap and cost model for 3D chips with through-silicon vias. 2009, building a 3D IC line with thermocompression bonding, fusion bonding, temporary bonding, and chip-to-wafer bonding. (3-D ASIP 2005, 2007, 2008; VMIC 2006 & 2008, 3D-SIC 2007; IMAPS 2008, DATE 2009, BrightSpots 2009, Semicon West 2009)

bulletSemico

Research on end-use market drivers for 3D components.  (3-D ASIP 2004)

bulletSharp Corporation

Research on 3D packaging. (3-D ASIP 2004)

bulletSI2 (Silicon Integration Initiative)

Research to improve interoperability and integration across silicon design flows. (3-D ASIP 2009)

bulletSoitec

Research on wafer-level circuit stacking, mostly SOI wafers, using handler wafers and silicon oxide bonding. 2009: announced Smart Stacking™, low-temp transfer of thinned layers; also working on direct metal bonds; working with IBM on thinning & bonding for 3D image sensor technology; working with CEA-Leti on coupled oxide 3-D process; research on gallium nitride and other substrates for bonding. (Semicon West 2009, 3-D ASIP 2009)

bulletSonoscan

Research on imaging stacked wafer pairs to detect bond defects.

bulletSRC (Semiconductor Research Corporation) Research consortium

Coordinates academic "pre-competitive" research, including 3D process structures and 3D integration. (3-D ASIP 2005)

bulletST-Ericsson

Research on 3D for mobile phones and full 3D-IC integration for wireless technology. (3-D ASIP 2009)

bulletStanford University

Research on 3D IC interconnects, integrity, performance, epitaxial growth, thermal issues, hybrid devices, 3D FPGAs, etc. (Great Lakes Symposium of VLSI, International Symposium on System Designs (ISPD), and IAB, all in 2004; VMIC 2004 thru 2007; 3-D ASIP 2004 thru 2006)

bulletSTATS ChipPAC

Research on thru-silicon vias, micro-bumping, wafer thinning and bonding, 3D wafer level integration. (3-D ASIP 2004, 2006, 2007, 2009; IMAPS 2007 & 2008)

bulletSTMicroelectronics (STMicro)

Research on wafer-level and chip-level alignment; covalent bonding; vertical communication bit-rates; 3D CMOS image sensors. 2009: announced 3D-IC demonstrator (with CEA-Leti). (3-D ASIP 2006, IITC 2007, IMAPS 2008 & 2009, DATE 2009)

bulletSun Microsystems

Research on 3D interconnect: power, bandwidth, architectures. (3-D ASIP 2004)

bulletSynopsys

Research on design tools. (3-D ASIP 2008, BrightSpots 2009)

bulletTechnische Universität Berlin

Research on chip-in-polymer technology. (MRS 2006, IMAPS 2007 & 2008)

bulletTessera

Research on 3D chip-scale packaging. Hosted 3D packaging symposium in 2003. (3-D ASIP 2004 & 2007, IMAPS 2009, Semicon West 2009)

bullet Tohoku University

Research on 3D technology including wafer stacking with adhesive and micro-bump bonds, and die-to-wafer bonding with self-assembly; developed a 3D artificial retina, various 3-layer chips (with Mitsubishi, MIT, ZyCube). (VMIC 2004 & 2008, 3-D ASIP 2005, MRS 2008, IITC 2008)

bulletTokyo Electron

Research (with SEMATECH) on 3D interconnect.

bulletToshiba

Research on chip-stacking with copper bump bonding and through vias; 3D memory cells and CCDs (tested 2005); inter-level "crossbar" technology, 3D NAND Flash, 3D cache systems. (3-D ASIP 2004 thru 2007, VMIC 2008, ISSCC 2009, DATE 2009)

bulletTSMC (Taiwan Semiconductor Manufacturing Company)

Research on "via-first" TSV fabrication, die-to-wafer and wafer-to-wafer bonding with copper thermo-compression. (IITC 2008)

bulletUCLA (VLSI CAD LAB group)

Research on 3D thermal-aware design tools (with DARPA, CFDRC). (VMIC 2006)

bulletUniversity of Arkansas

Research on integrated system development for 3D VLSI. (IMAPS 2008 & 2009)

bulletUniversity of Bergamo, Italy

Research on vertically integrated pixel detector (Front-End Electronics 2009)

bulletUniversity of Bonn, Germany

Research on 3D-IC sensors (Front-End Electronics 2009)

bulletUniversity of Pavia, Italy

Research on 3D-IC active pixel sensors (Front-End Electronics 2009)

bulletUniversity of Perugia, Italy

Research on 3D sensors and detectors. (Pixel 2008, Front-End Electronics 2009)

bulletUniversity of Rochester

Research on TSV, clock & power distribution in 3D ICs. (VMIC 2008, DATE 2009, 3-D ASIP 2009)

bulletUniversity of Tokyo, Japan

Research on 3D NAND Flash (ISSCC 2009)

bulletVertical Circuits

Research on wafer stacking; vertical connectors are applied to the die edges. (3-D ASIP 2007)

bulletXilinx

Research on die stacking, 3D programmable "system-in-package" devices; working with DARPA. (3-D ASIP 2006, 2008)

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Market Research, Analysis, Consulting, Reporting

bulletFrancoise in 3D

Blog by Francoise von Trapp; "following the course of 3D integration"

bulletPerspectives from the Leading Edge (Semiconductor International)

Blog by Philip Garrou; 3D IC news and progress (3-D ASIP 2008, IMAPS 2008 & 2009)

bulletPrismark Partners

Monitors and reports on 3D IC technology. (3-D ASIP 2006)

bulletTechSearch International

(3-D ASIP 2007 thru 2009; GBC 2009)

bulletYole Developpement

Market research & reporting; publishes monthly "Micronews" and "i-Micronews" (3-D ASIP 2007 thru 2009; IMAPS 2008 & 2009, BrightSpots 2009)

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Copyright © 2004-2009 Tezzaron® Semiconductor. All rights reserved.  Revised: January 27, 2010
 

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