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Error-resistant 3T-iRAM® technology |
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300 MHz to 400 MHz clock |
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Separate independent Read and Write data ports |
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Concurrent Read/Write transactions are supported |
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Dual DDRII+ interface (data rate is twice clock speed) |
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Pin-compatible with QDRII+™ SRAMs |
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2.0 clock cycle Read latency |
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Burst of 4 Read and Write |
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Separate Port Selects for depth expansion |
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Synchronous internally self-timed Writes |
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Full data coherency |
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2 input clocks and 2 echo clocks |
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1.8 V ±100 mV core power supply |
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1.5 V ±100 mV I/O power supply |
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HSTL I/O with variable drive output buffers |
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ZQ pin for programmable output drive strength |
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QVLD pin indicates valid output data |
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IEEE 1149.1 JTAG-compliant Boundary Scan |
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Lead-free JEDEC-standard pinout and package |
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165-bump 15mm x 17mm BGA, 1 mm bump pitch |
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Pin-compatible with 9Mb, 18Mb, 36Mb, and 144Mb devices |
3T-iRAM® is a unique type of dynamic memory. Tezzaron has crafted these pseudo-static devices
to provide entirely SRAM-compatible interfaces and timing. The unique design of these 3T
memories provides soft error rates up to 10 times lower than equivalent high-speed,
high-density SRAMs, while maintaining drop-in compatibility.
QTRII+™ (Quad Transfer Rate II+) is a Separate I/O architecture that makes these devices
drop-in compatible with QDRII+™ SRAMs. It uses two separate ports for Read and Write
operations with dedicated data input and output pins and a common address bus. This completely
eliminates the “bus turn-around” time required in Common I/O devices. To maximize throughput,
both data ports use DTRII+™ (Double Transfer Rate II+) interfaces.
These pipelined synchronous 72Mb devices employ two input register "K" clocks.
These are independent single-ended clock inputs, not differential inputs, for precise data
timing. Read and Write addresses are latched on alternate rising edges of the K clock. Data
transfers (input and/or output) occur on the rising edges of both clocks. Two echo clocks
simplify data capture for Reads. Writes are self-timed with on-chip circuitry.
These devices always transfer data in four packets. A0 and A1 are internally set to 0 for the
first read or write transfer and automatically incremented by 1 for each of the next three
transfers.
