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Error-resistant 3T-iRAM® technology |
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300 to 375 MHz clock for high bandwidth |
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Read latency of 2 clock cycles |
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DTRII+™ Interface with Common I/O bus |
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Fully pin-compatible with DDRII+™ SRAMs |
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Lead-free JEDEC-standard pinout and package |
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Burst of 2 Read and Write (Byte Writes) |
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1.8 V core power supply, 1.5 V I/O |
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Synchronous internally self-timed Writes |
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ZQ pin for programmable output drive strength |
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QVLD pin indicates valid output data |
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DLL for accurate data placement |
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IEEE 1149.1 JTAG-compliant Boundary Scan |
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165-bump 15mm x 17mm BGA, 1 mm bump pitch |
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Pin-compatible with 9Mb, 18Mb, 36Mb, and 144Mb devices |
3T-iRAM® is a unique type of dynamic memory. Tezzaron has crafted these pseudo-static devices
to provide entirely SRAM-compatible interfaces and timing. The unique design of these 3T
memories provides soft error rates up to 10 times lower than equivalent high-speed,
high-density SRAMs.
DTRII+™ is a double transfer rate interface that is implemented with Common I/O architecture
in these devices, making them drop-in compatible with DDRII+ SRAMs.
These synchronous pipelined 72Mb 3T-iRAM devices employ two register clocks. These are
independent single-ended clock inputs, not differential inputs. All synchronous inputs pass
through registers controlled by these clocks. Accesses are initiated on the rising edge of the
positive clock and data is registered or driven on the rising edges of both clocks. Write
(input) and Read (output) data share the same data pins. Data outputs are tightly matched to
two free-running echo clocks which are referenced with respect to the register clocks. Data
inputs are controlled by self-timed Write circuitry.
These devices always transfer data in two packets. A0 is internally set to 0 for the first
transfer of a data burst and automatically incremented to 1 for the second transfer.
