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Error-resistant 3T-iRAM® technology |
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DTRII™ Interface with Common I/O bus |
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Fully pin-compatible with DDRII and SigmaCIO™ SRAMs |
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Lead-free JEDEC-standard pinout and package |
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Burst of 4 Read and Write (Byte Writes) |
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1.8 V +100/-100 mV core power supply |
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1.5 V or 1.8 V HSTL Interface |
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Pipelined read operation with self-timed Late Write |
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Fully coherent read and write pipelines |
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ZQ pin for programmable output drive strength |
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IEEE 1149.1 JTAG-compliant Boundary Scan |
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165-bump 15mm x 17mm BGA, 1 mm bump pitch |
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Pin-compatible with 9Mb, 18Mb, 36Mb, and 144Mb devices |
3T-iRAM® is a unique type of dynamic memory. Tezzaron has crafted these pseudo-static devices
to provide entirely SRAM-compatible interfaces and timing. The unique design of these 3T
memories provides soft error rates up to 10 times lower than equivalent high-speed,
high-density SRAMs.
DTRII™ is a double
transfer rate interface that makes these devices drop-in compatible with
DDRII and SigmaCIO™ SRAMs.
These synchronous 72Mb
3T-iRAM devices employ two input register clocks
. The user can manipulate two output register clocks
quasi-independently
. These clocks are four independent single-ended clock inputs, not
differential inputs. If the output clocks are tied high, the input clocks
are routed internally to fire the output registers instead.
These devices always transfer data in four packets, but addressing is handled differently for
x9 parts than for x36 and x18 parts:
For x36 and x18, when a new address is loaded, A0 and A1 preset an internal 2 bit address
counter. The counter increments by 1 for each beat of a burst of four data transfer,
wrapping to 00 after reaching 11.
For x9, when a new address is loaded, the LSBs are internally set to 00 for the first read
or write transfer, and incremented by 1 for the next three transfers.
