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Error-resistant 3T-iRAM® technology |
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Multi-level Bit Armor™ data protection (internal ECC, periodic scrubbing,
error reporting) |
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NBT (No Bus Turnaround) functionality for zero wait Read-Write-Read bus usage |
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Fully pin-compatible with pipelined NtRAM™, NoBL™ and ZBT™ |
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2.5 V ±10% core power supply, 1.8 V or 2.5 V I/O supply |
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User-selectable drive strength |
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IEEE 1149.1 JTAG-compatible Boundary Scan |
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User-selectable Linear or Interleaved Burst mode |
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Pin-compatible with 2/4/9/18/36Mb devices |
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Byte write operation (9-bit Bytes) |
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3 Chip Enable signals for easy depth expansion |
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ZZ pin for automatic power-down |
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Lead-free JEDEC-standard 119- and 165-FBGA packages |
3T-iRAM® is a unique type of dynamic memory. Tezzaron has crafted these pseudostatic devices
to provide entirely SRAM-compatible interfaces and timing. The unique design of these 3T
memories provides soft error rates up to 10 times lower than equivalent high-speed,
high-density SRAMs. In addition, these parts incorporate Tezzaron’s multi-level Bit Armor™
system for error rates up to 1000 times lower than traditional SRAMs. Bit Armor incorporates
user-transparent periodic error scrubbing and ECC with error reporting.
The TSC2E72T18/36 is a 72Mbit synchronous memory device that functions much like ZBT, NtRAM,
NoBL, and other pipelined read/double late write SRAMs – it exploits all available bus
bandwidth by eliminating “deselect cycles” when the device is switched from read to write.
As in all synchronous devices, address, data inputs, and read/write control inputs are
captured on the rising clock edge. The Burst order control pin must be tied to a power rail
for proper operation. Asynchronous inputs include Sleep mode enable and Output Enable. Output
Enable can override the synchronous control of the output drivers to turn them off at any
time. Write cycles are internally self-timed and initiated by the rising clock edge; this
eliminates the complex off-chip write pulse generation required by asynchronous SRAMs and
simplifies input signal timing.
The TSC2E72T18/36 incorporates a rising-edge-triggered output register. For read cycles,
output data is stored in the edge-triggered output register during the access cycle and then
released to the output drivers at the next rising clock edge.
