Tezzaron's groundbreaking FaStack® technology creates 3D memory devices with vast densities,
superior speeds, and phenomenal error protection. FaStack memory devices contain many layers
of memory cells stacked on top of one control and interface layer, greatly increasing memory
density. Increased density allows system developers to use fewer components, create simpler
designs, reduce cost and power requirements, make testing easier, and still keep pace with
the ever-accelerating demand for more computer memory.
Process Separation
The FaStack design places control and interface logic on a piece of silicon entirely
separate from the memory cells. Logic elements are manufactured on dedicated wafers,
optimized by using CMOS high-speed processes that create high-performance transistors.
Memory wafers are optimized by using a different, high-density NMOS process that creates
high-quality capacitors. The result is faster, denser memory without any radical changes to
design.
Memory Density
Using four layers of memory, FaStack can stack 1 Gbit of memory in the same footprint used
by 256 Mbit chips – a density increase of 300%. With up to thirty-two memory cell layers per
device, the memory capacity of a single FaStack 3D memory package can equal thirty-two devices
of the same technology from any other manufacturer, with exactly the same footprint.
Memory Speed
FaStack/3T-iRAM® is blazingly fast, with an access
time of 4 ns. Even with ordinary DRAM, FaStack can achieve an impressive 27 ns access time.
Much of this speed is due to the process separation described above. In addition, using short
vertical interconnects (Super-Vias) in place of long horizontal wires allows faster access to
all the memory cells in a high-capacity chip.
Endurance and Soft Error Resistance
No matter which memory technology is used in a FaStack product, its endurance and its
resistance to soft errors will be greatly increased. The reason for this is Tezzaron’s
patented Bi-STAR® built-in self test and repair
circuitry. One entire layer of each FaStack 3D memory device is devoted to controller and
interface components, providing more room for logic and circuitry than any single-layer
memory chip. This extra silicon area incorporates an independent microcontroller and other
circuitry, including Bi-STAR, which improves yield, eliminates expensive test and repair
steps, and greatly increases the reliability of FaStack parts.
Memory Interface
The first FaStack parts are socket-compatible with standard devices, providing greater
density and reliability without any design changes or BIOS modifications. Because the
interface logic is confined to the controller layer, new interfaces can be implemented
quickly and easily, with no impact on the memory cell wafers.
Future Generations of FaStack Memory
Early FaStack 3D memory parts were stacked SRAM devices. Future generations of FaStack
products will stack 3T-iRAM, and may stack other memory technologies as the market demands.
Tezzaron also intends to implement silicon processes that build smaller, denser features;
these processes will lead to new, higher-density generations of FaStack products. Eventually,
FaStack will be used to stack layers of TufFRAM®.
