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Click on any picture to see a larger image
| This circuit design contains a simple FPGA. It is designed to be stacked in
identical layers, allowing tests of the interconnect in a 3D FPGA. |
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| Here is one circuit layer, fabricated in a 180-nm process. Two-layer parts were built and
tested (photos not available). |
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Copyright © 2005-2009 Tezzaron® Semiconductor. All rights reserved. Revised:
April 08, 2009
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