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"Martin" 3D MPW Project

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The "Martin" project co-designed and built 3D-IC prototype devices in collaboration with 20 participants.  Some devices were built as two-layer chips, others were integrated with 3D memory chips to create multi-layer 3D-ICs.

More photos will be added to this page as they become available.

Click on any picture to see a larger image

This is a finished 2-wafer stack with aluminum back metal, ready for dicing. 2011-06-03 09.18.11.jpg (94895 bytes)
Late June 2011:  Four of the first two-layer chips, each 5mm x 13mm FirstMartinChips.jpg (56406 bytes)
A closer look... FirstMartinChips2.jpg (92209 bytes)
Enlarged view of two chips. FirstMartinChips3.jpg (105743 bytes)
Early July 2011:  These nine photos show the next set of two-layer chips:

B2.jpg (17153 bytes)  B2R.jpg (18205 bytes)  C2.jpg (15857 bytes)  D1.jpg (11040 bytes)

D2.jpg (6341 bytes)  D3.jpg (17332 bytes)  E1.jpg (6757 bytes)  E3.jpg (15349 bytes)  F2.jpg (9292 bytes)
Cross-section SEM showing two bonded layers.
   Two patterned bands of small dense lines are circuitry.
   Wide dark band near center is the face-to-face bond with bright bondpoints.
   Four bright vertical lines above the circuitry are TSVs.
   Bright horizontal line at top is aluminum surface layer.		 SEM002crop.jpg (318141 bytes)
 
Copyright © 2011 Tezzaron® Semiconductor. All rights reserved.  Revised: December 27, 2011
 

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