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Press Releases

9 Dec. 2011, Honeywell and Tezzaron to Build Rad Hard 3D-ICs

6 Dec. 2011, A*STAR IME and Tezzaron Team Up To Develop 2.5D/3D Through-Silicon Interposer Technology

22 July 2011, Ten Custom 3D-ICs From Tezzaron

12 June 2007, Chartered, Tezzaron Team Up to Deliver Ultra High-Speed Memory Solution

19 Sept. 2005, Tezzaron Inks Sales Rep Contracts for SRAM

9 May 2005, Tezzaron, PICC to Collaborate on 3D Flash Memory

28 Feb. 2005, Ziptronix®, Tezzaron® Announce Alliance for 3D ICs

24 Jan. 2005, Tezzaron® Unveils 3D SRAM

23 Dec. 2004, 3D Semiconductors Poised for Revolution

6 Dec. 2004, Third Dimension Triples Processor Speed

22 Nov. 2004, Tezzaron Launches RAM in a New Dimension

10 May 2004, Tezzaron Wins $1M in Purchase Orders

14 April 2004, Tezzaron Announces Commercial 3D ICs

18 Aug. 2003, New Memory Technology is World's Fastest

News Articles

20 December 2010, Bob Patti, Tezzaron Semiconductor, at the RTI 3D Architectures for Semiconductor Integration and Packaging 2011 (Video)

3 June 2011, Mentor Graphics Works With Tezzaron and MOSIS on 3D-IC Prototyping Service (Mentor press release)

14 April 2011, Tezzaron Reports Outstanding 3D Success at ISPD (MonolithIC 3D)

16 December 2010, The Future is Here ... Bob Patti: 3D @ Tezzaron (EDA Confidential)

12 January 2010, 2009 SEMI Awards for North America Bestowed on Robert Patti of Tezzaron Semiconductor (SEMI press release)

10 December 2009, Tezzaron tips 3-D memory, signs up SVTC (EE Times)

8 December 2008, Labs and industry perfect 3-D chip(Symmetry)

10 July 2008, 3-D Chip Stacks Standardized (EE Times)

Other news coverage

White Papers and Articles

Building 3D-ICs: Tool Flow and Design Software -- an EE Times article in two parts (2011)

3D-ICs and Integrated Circuit Security -- A white paper (2008) (1.27 MB)

3-D Power Savings -- A discussion (2007)(435 KB)

Techniques for Producing 3D ICs with High-Density Interconnect A presentation from the 2004 VLSI Multi-Level Interconnection Conference (VMIC) (4,052 KB)

Soft Errors in Electronic Memory -- A white paper (87 KB) (updated January 2004)

DRAM Pricing -- A white paper (2002) (1,604 KB)

Management Team

Management Photos and Bios

James T. Ayers, Jr., Chairman, CEO; Director, Tezzaron (Singapore) Pte Ltd

Savely Burd, CFO

Robert Patti, CTO, VP of Design Engineering; Director, Tezzaron (Singapore) Pte Ltd

Dr. Subhash Gupta, VP of Corporate Strategies

Greg Krasick, VP of Sales

Dr. Kenneth S. Su, VP of Business and Technology Development in Asia

Dr. Sangki Hong, Operations Director of Process Development, Tezzaron (Singapore) Pte Ltd

Product and Technology Images

(hi-res versions may be available on request)

3D-IC MPW Project (2011)

3D-IC Microprocessor Demonstration Video (2005)

3D-IC FPGA Prototype (May '05)

3D-IC Sensor Prototype (May '05)

3D-IC SRAM Prototype (January '05)

Wafer Pair with Circuitry and Super-Contacts (February '05)

3D-IC Processor (December '04)

3D-IC RAM Prototype (November '04)

Interconnected Wafer Stack with Super-Vias (June '03)

3T-iRAM® Prototype Chips (PSiRAM) (July/August '03)

Other photos

Media Contact

Gretchen Patti
gpatti@tezzaron.com
Phone: +1-630-505-0404 x109
Fax: +1-630-505-9292

Copyright © 2008-2011 Tezzaron® Semiconductor.  All rights reserved.  Revised: January 18, 2012