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World's first 3D-IC processor |
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Up to 90% power reduction |
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Industry standard 8051 / 8031 software compatible |
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RISC architecture with up to x12 speed advantage / MHz over traditional 8051 family
devices |
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Four speed grades: 100, 150, 180, and 200 MHz |
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128, 256, or 512KB of additional high-speed FaStack® SRAM memory |
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IEEE 754-compliant floating point coprocessor for full arithmetic capabilities - up to 100
MFlops |
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Extended 32-bit computing functions including population counter, leading zero counter, and
floating-point comparator |
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Dual data pointers for fast data block moves |
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Up to 200 MIPS and 100 MFlops |
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132 PGA or 128 BGA packaging |
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Full 8051-compatible architecture including: |
* Four 8-bit bi-directional ports
* 256 Bytes of "Scratch Pad" memory
* Three 16-bit timer/counters
* Interrupt controller with 12 interrupt sources and 4 priority levels
* 15-bit programmable watchdog timer
* Core 8-bit arithmetic logic unit and 16-bit multiplication division unit
* Two full-duplex serial ports
* Four capture/compare units to generate pulse width modulated signals
* Special Function Register (SFR) interface, serving up to 50 SFR devices
Tezzaron Semiconductor's TSCR8051Lx micro-controllers feature layers of stacked integrated
memory. These 8-bit micro-controllers are software compatible with the millions of devices
that have been produced since Intel® introduced the 8051 line in 1980. The TSCR8051Lx executes
all ASM51 instructions and uses the same instruction set as the 8031.
The TSCR8051Lx uses a Reduced Instruction Set Computer (RISC) core so that many of its
instructions are executed in a single clock cycle. This provides a significant speed advantage
over traditional 8051 devices that execute an instruction every twelve clock cycles. With
clock speeds of up to 200 MHz, the Tezzaron devices are 8051 performance leaders.
The TSCR8051Lx uses Tezzaron's patented FaStack® wafer stacking technology to bond one or more
layers of high-speed SRAM over the processor, providing additional Data and Program memory. In
the TSCR8051L2, a single SRAM layer provides 128KBytes of partitionable Data and Program
memory; in the TSCR8051L3, there are two layers of SRAM (256KBytes); in the TSCR8051L5, four
layers (512KBytes).
The TSCR8051Lx features extended 32-bit capabilities including an IEEE 754-compliant
floating-point coprocessor with comparator, a multiply/divide unit, a population counter, and
a leading-zero counter.
This processor is supported by Keil® Software
